An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects

This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of different test speeds, if available, can be combined to further improve the diagnosis results. Experimental results on five advanced industrial designs show the accuracy of the proposed technique.