On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test

Memory interface speed has been rapidly increasing to overcome the performance gaps between microprocessor and memory. Testing the I/O timing parameters at-speed has become a challenge because of the limitations on the test clock frequencies provided by low-cost testers. This paper presents a technique to generate a dual-capture signal with a programmable delay for both rising and falling transitions, which effectively tests double-data rate memory interface timing. The relative delay difference between data and clock paths is measured for the I/O timing test instead of using complicated test vectors. The test clock frequency is programmed in a wide operating range with 20 ps resolution. The proposed on-chip programmable double-capture generator can be also easily integrated with the current scan-based delay test methods. The scheme has low area overhead, low design effort, and is also compatible with low-cost testers.