Title :
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data
Author :
Xiang, Dong ; Chen, Zhen
Author_Institution :
Sch. of Software, Tsinghua Univ., Beijing, China
Abstract :
A new test application scheme is proposed for low-power scan testing, which is able to compress test data significantly. A combination of a scan architecture and an existent test compression scheme can compress test data even better. Test power can be reduced greatly based on the new test application scheme, according to which only a subset of scan flip-flops shifts a test vector or captures test responses in any clock cycle. Test response data can be another important problem. A new test response compaction scheme called selective test response collection is proposed to reduce test response data. Selective test response collection combines with a structure-based test response compactor, according to which many test response data can be dropped. Experimental results show that the proposed test application scheme can efficiently reduce test power, compress test stimulus data, and compact test response data while test application cost can be well-controlled.
Keywords :
data compression; flip-flops; logic testing; low-power electronics; clock cycle; low-power scan testing; scan architecture; scan flip-flops shifts; selective test response collection; structure-based test response compactor; test application scheme; test compression scheme; test response compaction scheme; test response data; test stimulus data compression; test vector; well-compressed test data; Circuit faults; Clocks; Compaction; Equations; Testing; Vectors; Vegetation; low power; test compaction; test compression; test data volume;
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
Print_ISBN :
978-1-4577-1984-4
DOI :
10.1109/ATS.2011.74