Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates

Memories constitute increasing proportions of most digital systems and memory-intensive chips lead the migration to new nanometer fabrication processes. With each process generation, process variations and defect rates are increasing, at the same time, cells are becoming more susceptible to soft errors with technology shrink. SRAMs will thus require increasing numbers of spares and stronger error correcting codes (ECCs), incurring higher area overheads and access-time penalties. Our overall objective is to develop new systematic approaches for designing defect-tolerant 6T-SRAMs optimized in terms of yield-per-area under high defect rates and high soft error rates, for given soft-error resilience and access-time requirements. In this paper, we analyze the key tradeoffs associated with using different numbers of spares and ECCs with different strengths. In addition to considering the usual role of each -- i.e., spares to combat defects and ECC to combat soft errors -- we also consider the ability of ECC to combat those defects which cannot be masked using available spares. We develop a new model that captures the benefits -- yield and resilience to soft errors -- of spares and ECC in an integrated manner. We also characterize area and access time overheads of the spares and the ECC scheme. We then integrate above into a framework to design 6T-SRAMs that optimizes yield-per-area. We demonstrate that the proposed approach provides dramatic improvements in yield and yield-per-area without compromising resilience to soft errors.