Title :
FinFETs for nanoscale CMOS digital integrated circuits
Author_Institution :
Adv. Technol. Group, Synopsys, Inc., Mountain View, CA, USA
Abstract :
Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs.
Keywords :
CMOS digital integrated circuits; MOSFET; leakage currents; nanoelectronics; CMOS digital integrated circuits; CMOS technologies; FinFET technology; device-to-device variability; gate length; leakage current; nanoscale integrated circuits; nonclassical transistor structures; standby power consumption; transistor performance; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Energy consumption; FETs; FinFETs; Integrated circuit technology; Leakage current; MOSFET circuits; Transistors;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560065
