DocumentCode :
2799704
Title :
On Using Design Partitioning to Reduce Diagnosis Memory Footprint
Author :
Fan, Xiaoxin ; Tang, Huaxing ; Reddy, Sudhakar M. ; Cheng, Wu-Tung ; Benware, Brady
Author_Institution :
Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
fYear :
2011
fDate :
20-23 Nov. 2011
Firstpage :
219
Lastpage :
225
Abstract :
Recently statistical yield learning based on volume diagnosis has become popular. Volume diagnosis requires a large amount of diagnosis results to be produced within a reasonable time. However, it is challenging to achieve the desired throughput for modern designs with continuously increasing size. In this paper, we propose a method to partition a design under diagnosis into blocks together with a diagnosis flow at the block level. The diagnosis throughput is improved because more diagnosis jobs can be run concurrently and each job runs faster due to the reduced memory. A measure is also proposed to estimate the impact on diagnosis caused by design partitioning. Experimental results on benchmark circuits and several industrial designs show that diagnosis using circuit blocks has minimal impact on diagnosis accuracy and resolution. It is also demonstrated that the proposed measure is a good metric in predicting the impact on diagnosis.
Keywords :
fault diagnosis; integrated circuit design; integrated circuit yield; logic design; benchmark circuits; block level; circuit blocks; design partitioning; diagnosis flow; diagnosis memory footprint; diagnosis throughput; industrial designs; statistical yield learning; volume diagnosis; Accuracy; Algorithm design and analysis; Bismuth; Circuit faults; Dictionaries; Logic gates; Partitioning algorithms; design partitioning; logic diagnosis; volume diagnosis; yield learning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
ISSN :
1081-7735
Print_ISBN :
978-1-4577-1984-4
Type :
conf
DOI :
10.1109/ATS.2011.45
Filename :
6114542
Link To Document :
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