DocumentCode :
2799734
Title :
Yield Improvement and Test Cost Optimization for 3D Stacked ICs
Author :
Hamdioui, Said ; Taouil, Mottaqiallah
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear :
2011
fDate :
20-23 Nov. 2011
Firstpage :
480
Lastpage :
485
Abstract :
Three-Dimensional Stacked IC (3D-SIC) is an emerging technology promising many benefits, such as heterogeneous integration, reduced latency and power consumption. Realizing higher compound yield and overall low cost are the driving forces of the success of such a technology. This paper addresses these two topics. First, two yield improvement schemes will be discussed: wafer matching and layer redundancy. Wafer matching is a technique that can be applied when Wafer-to-Wafer (W2W) stacking is used to fabricate 3D-SICs, this stacking approach provides many advantages such as high throughput, thin wafer and small die handling, and high TSV density, however, it suffers from low compound yield as compared with other stacking processes. Layer redundancy, on the other hand, is based on adding redundant layer(s) to the stacked IC to replace the faulty irreparable dies in the stack. It can be applied only when similar dies are stacked as it is the case for stacked memories. Experiment results for both wafer matching and layer redundancy will be presented and compared, they show that both wafer matching and layer redundancy significantly improve the yield and therefore reduce the cost per 3D-SIC. Second, test cost optimization will be covered. During the manufacturing of 3D-SICs, tests can be applied at different moments such as before the stacking process, during the creation of each partial stacked IC, after the creation of the complete stack, etc. This results into a huge number of test flows. A framework covering different test flows will be discussed. In addition, an appropriate cost model able to identify the most cost-effective test flow will be presented. The simulation results show that test flows with the pre-bond testing significantly reduce the overall cost, that a cheaper test flow does not necessary results in lower overall cost, and that the best cost-effective test flow strongly depends on the stack yield, hence, adapting the test according the stack yield is - he best approach to use.
Keywords :
integrated circuit testing; integrated circuit yield; optimisation; redundancy; three-dimensional integrated circuits; 3D-SIC manufacturing; TSV density; cost-effective test flow; layer redundancy; pre-bond testing; small die handling; stack yield; stacked memories; test cost optimization; three-dimensional stacked IC; wafer matching; wafer-to-wafer stacking; yield improvement; Compounds; Integrated circuit modeling; Manufacturing; Redundancy; Semiconductor device modeling; Stacking; Three dimensional displays; 3D Stacked IC; Layer Redundancy; Test Flows; Yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
ISSN :
1081-7735
Print_ISBN :
978-1-4577-1984-4
Type :
conf
DOI :
10.1109/ATS.2011.88
Filename :
6114544
Link To Document :
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