Title :
Test method for IC electrical overstress hardness estimation
Author :
Skorobogatov, P.K.
Author_Institution :
Specialized Electron. Syst., Moscow, Russia
Abstract :
A test method to estimate the electrical overstress (EOS) hardness of ICs is presented. It is based on unification of test conditions. The advantage of the method is the possibility it gives to compare the EOS hardness of different ICs. A specialized test installation has been designed to estimate the hardness of different ICs to EOS, including transient and permanent effects. Experimental data for digital bipolar IC and 4K×1 CMOS RAM EOS hardness are given including the effects of upset, latch-up and catastrophic failure
Keywords :
electrostatic discharge; integrated circuit testing; CMOS RAM; IC electrical overstress hardness testing; catastrophic failure; digital bipolar IC; latch-up; upset; Dielectric breakdown; Earth Observing System; Electric breakdown; Equivalent circuits; Integrated circuit testing; Pins; Power supplies; Semiconductor device breakdown; Signal analysis; Voltage;
Conference_Titel :
Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on
Conference_Location :
Cannes
Print_ISBN :
0-7803-4071-X
DOI :
10.1109/RADECS.1997.698882
