Title :
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
Author :
Shekhar, Namrata ; Kalla, Priyank ; Enescu, Florian ; Gopalakrishnan, Sivaram
Author_Institution :
Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake, UT, USA
Abstract :
This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finite integer rings of residue classes Z2m. The verification problem then reduces to that of checking equivalence of multi-variate polynomials over Z2m. This paper exploits the concepts of polynomial reducibility over Z2m and derives an algorithmic procedure to transform a given polynomial into a unique canonical form modulo 2m. Equivalence testing is then carried out by coefficient matching. Experiments demonstrate the effectiveness of our approach over contemporary techniques.
Keywords :
digital arithmetic; equivalence classes; formal verification; integrated circuit design; logic design; polynomials; RTL descriptions; canonical form modulo; coefficient matching; datapath-oriented designs; equivalence testing; equivalence verification; finite ring algebra; fixed-size bit-vectors; multivariate polynomials; polynomial algebra; polynomial computations; polynomial datapaths; Algebra; Arithmetic; Cities and towns; Design optimization; Digital signal processing; Mathematical model; Mathematics; Polynomials; Signal processing algorithms; Statistics;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560081