Title :
RTL SAT simplification by Boolean and interval arithmetic reasoning
Author :
Parthasarath, G. ; Iyer, M.K. ; Cheng, K.-T. ; Brewer, F.
Author_Institution :
California Univ., Santa Barbara, CA, USA
Abstract :
We present a method that combines interval-arithmetic (IA) and Boolean reasoning with structural hashing for simplifying SAT problems on circuits expressed at the register-transfer level. We demonstrate that simple transformations based on interval-arithmetic operations can significantly reduce the complexity of the problem. We identify cases where the inherent over-approximations in IA operations can be reduced. We demonstrate that these techniques can significantly reduce RTL-SAT instances in size and runtime.
Keywords :
Boolean functions; computability; digital arithmetic; logic design; Boolean reasoning; RTL SAT simplification; interval arithmetic reasoning; interval-arithmetic operations; register-transfer level; structural hashing; Arithmetic; Boolean functions; Circuit synthesis; Design automation; Electronic design automation and methodology; Encoding; Minimization; Runtime;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560082