Dielectric film stress influences on GaAs MESFET gate breakdown

It has been found that GaAs MESFET gate breakdown voltages (BVGD) can be reduced by as much as 50% by deposition of stressed overlayer dielectric films. These films do not have to be in contact with the GaAs surface and do not measurably alter the electrical characteristics of the GaAs/dielectric interface. The effect is reversible, leading to the identification of the cause as being the piezoelectric fields induced in the underlying GaAs. The one-dimensional line load model typically used to calculate piezoelectric charge density tends to overestimate the effect. An improved distributed edge force model that provides a simple analytical solution and good quantitative agreement with experimental data is proposed.<>