Noise margin analysis for dynamic logic circuits

We consider the problem of noise margin analysis for dynamic logic circuits. Because such circuits operate in multiple phases, their noise immunity is also time varying. We formulate noise margin analysis as a non-linear optimization problem where we find the smallest disturbance waveform that results in a qualitative change in the behavior of the circuit. We present a practical method for solving these optimization problems based on deriving a sensitivity matrix for the small-signal response of the circuit. We use our approach to compare the robustness of static CMOS gates, self-resetting domino, and output prediction logic.