High speed 8:1 multiplexer and 1:8 demultiplexer ICs using GaAs DCFL circuit

Author

Tanaka, K. ; Shikata, M. ; Kimura, T. ; Sano, Y. ; Akiyama, M.

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1991

fDate

20-23 Oct. 1991

Firstpage

229

Lastpage

232

Abstract

An 8:1 multiplexer and 1:8 demultiplexer chip set composed of GaAs direct-coupled FET logic (DCFL) has been designed and fabricated. The circuits were designed with tree type architecture and used memory cell type flip-flop (MCFF) as a flip-flop. Self-aligned GaAs MESFETs with a gate length of 0.5 mu m were used in these ICs. Both circuits operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V.<>

Keywords

III-V semiconductors; field effect integrated circuits; flip-flops; integrated logic circuits; multiplexing equipment; 1.5 W; 1.9 W; 1:8 demultiplexer ICs; 2.0 V; 8:1 multiplexer ICs; DCFL circuit; GaAs; III-V semiconductors; direct-coupled FET logic; gate length; memory cell type flip-flop; power dissipations; power supply voltage; tree type architecture; Circuits; FETs; Flip-flops; Gallium arsenide; Logic design; MESFETs; Memory architecture; Multiplexing; Power dissipation; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1991. Technical Digest 1991., 13th Annual

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-0196-X

Type

conf

DOI

10.1109/GAAS.1991.172679

Filename

172679