Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit: a statistical study

The intrinsic parameter fluctuations induced by random dopants into the characteristics of ultra-small CMOS devices have previously been studied using 3D numerical simulation of predominantly idealised devices (Asenov, 1998). In this paper we present a simulation study of intrinsic parameter fluctuations in carefully scaled realistic MOSFET devices at the next three technology nodes. The scaled devices are based on a real 35 nm transistor reported by Toshiba (Inaba et al., 2001) and depicted in the paper. It has been used to thoroughly calibrate our atomistic device simulator (Asenov, 1998). The paper illustrates the doping profile in the 35 nm reference device and in each of the scaled devices. The simulated I/sub D/-V/sub G/ characteristics of the reference device are in excellent agreement with measured data. The increased doping concentrations in the channels of the scaled devices are evident and provide the required short channel control in the 25 nm or 18 nm devices.