A Qualitative Approach to Optimize Coupling Capacitance for Simultaneously Switching Scenario in Coupled VLSI Interconnects

In DSM technology and beyond, the performance and correctness of the circuit cannot be assured without taking into consideration the multiple effects of interconnect parasitics. The inter wire parasitics i.e. mutual inductance and coupling capacitance are primary sources of crosstalk noise. In this paper, the optimization of coupling capacitance for delay and peak noise is carried out qualitatively. This optimization process is essential from the fact that propagation delay and peak noise in some cases show opposite behavior with change in coupling capacitance. For our study, two distributed RLC lines coupled inductively and capacitively are considered. A pair of interconnect lines each of 4 mm length and terminated by capacitive load of 30 fF with varying capacitive and inductive couplings are simulated. The SPICE waveforms are generated for simultaneous switching of inputs at far end of lines. The simulation is carried out for 130 nm, 1.5 V technology node. The width of driver PMOS and NMOS are taken as 70 μm and 35 μm respectively.