Manufacturing digital ICs with GaAs-the push for 100% yield

The strategy, implementation, and results of a yield enhancement program implemented during the start-up of a captive 100 mm GaAs IC manufacturing line for producing MSI to LSI complexity digital ICs for the Cray-3 Supercomputer System are described. This program was aimed at three major targets, namely, wafer breakage, parametric yield, and random defects associated with interconnect processes. The fruits of these efforts quickly resulted in sustained improvements which exceeded expectations in all target areas. In particular, wafer breakage rates are averaging below 7%. The development of a computerized, two step gate recess process has resulted in dramatic improvements in targeting pinchoff voltage and drain current such that parametric yields are now exceeding 90%. The issue of random defects and interconnect yields was addressed through the use of statistical yield enhancement drop-in PCMs.<>