An Explicit Delay Model for On-Chip VLSI RLC Interconnect

On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed, circuit complexity and an increase in interconnect length. In this paper, a novel closed form delay metric has been proposed for the on-chip VLSI RLC interconnect. The model has also been extended for the case when the time of flight of the input signal is comparable. It is started with a distributed RLC line model of the interconnect and analytically solved the resulting diffusion equation for the voltage response and 50% delay has been calculated and has been compared with SPICE delay and error is within 7%. The proposed method also calculates 50% delay by taking the time of flight into consideration and result is compared with SPICE and the average error has been found to be within 6%.