Title :
Modified SET D-Flip Flop Design for Low-Power VLSI Applications
Author :
Sharma, K.G. ; Sharma, Tripti ; Singh, B.P. ; Sharma, Manisha
Author_Institution :
Deptt. of Electron. & Commun. Eng., FET-MITS, Lakshmangarh, India
Abstract :
Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications.
Keywords :
VLSI; flip-flops; low-power electronics; low-power VLSI applications; modified SET D-flip flop design; portable applications; power efficient SET D-FF design; single edge triggered D-flip flop design; Clocks; Delay; Flip-flops; MOSFETs; Power demand; Substrates;
Conference_Titel :
Devices and Communications (ICDeCom), 2011 International Conference on
Conference_Location :
Mesra
Print_ISBN :
978-1-4244-9189-6
DOI :
10.1109/ICDECOM.2011.5738486
