A global optimization algorithm for the minimum test set of circuits

With the developing of the microprocessor and SOC (system on a chip) techniques, the research on the testability of mixed-signal (digital and analogue signal) circuits has became urgently requisite. The discrete event system (DES) theory gave a uniform and systematic approach for the testability and faulty-diagnosis problems of mixed-signal circuits. In this approach, one of the two main tasks is finding the minimum test set of the mixed-signal circuits. This paper illustrates a combinational optimization method based on the simulated annealing for the minimum test set of the mixed-signal circuits. Then there is the discussion about the convergence the algorithm´s searching process. Finally, some research directions are pointed out.