On the Scalability of Parallel Verilog Simulation

As a consequence of Moore´s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this paper, we examine the performance of a parallel Verilog simulator on four large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. We develop a parser for Verilog files enabling us to simulate in parallel all synthesizable Verilog circuits. We utilize four circuits as our test benches; the LEON Processor with 200 k gates, the OpenSparc T2 processor with 400 k gates and two Viterbi decoder circuits with 100 k and 800 k gates respectively. The simulator makes use of XTW and to our knowledge is the first Verilog simulator which can parse all synthesizable Verilog files. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800 k gates. The simulators´ performance was shown to be scalable.