Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

The increasing demand for high performance ICs and system on chip necessitates reliable methodologies for reducing pessimism in chip design. In this paper, we investigate how the frequency dependence of loop self inductance affects the RLC delay. We show that the pessimism in the estimation of RLC propagation delay could be as high as 30% if the frequency dependence of inductance is not considered properly. As a means of efficiently computing less pessimistic RLC delay values, we present an analytical model of frequency dependent loop self inductance that can be applied to model a wide range of real design scenarios. We demonstrate that our approach is computationally efficient and produces accurate and realistic (less pessimistic) delay values that lead to significantly improved system performance.