Full-band particle-based analysis of device scaling for 3D tri-gate FETs

In this paper, a 3D tri-gate SOI FET with a wrap around gate geometry is studied using a full-band particle-based simulation tool as stated in M. Saraniti et al. (1999) Tri-gate FETs show superior scalability over planar device structures, including a reduction of short channel effects based on F. Yang et al. (2002). The 3D gate structure of the tri-gate FET not only plays a role in reducing DIBL by shielding the electric field lines from the drain, but also improves gate-channel controllability.