Digital FIR Filter Optimization Using Toggle-Based Power Estimation Tools

In this paper one method of optimizing a digital finite impulse response (FIR) filter has been illustrated. The advantages and disadvantages of several architectures and of the circuit modeling were presented using a standard toggle-based method for the circuit power estimation, gate-level simulations and synthesis. We showed that we can achieve a significant power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for a 150nm technology but the method can be used for other technologies as well.