Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories

This paper presents a detailed investigation of the ISPP dynamics of charge-trap memory capacitors, considering not only the flat-band voltage but also the bottom oxide electric field and tunneling current evolution during programming. Differently from the floating-gate case, results on nitride-based memories show that the flat-band increase per step does not equal the step amplitude of the gate staircase, decreasing, moreover, as programming proceeds. As a consequence, the electric field and tunneling current through the bottom oxide are shown to largely increase. Using results at different temperatures and on samples with different stack compositions, this dynamics is explained in terms of a drop of the programming efficiency as more and more charge is stored in the nitride layer, due to the reduction of the number of free traps available for capturing the injected electrons.