DocumentCode
2801209
Title
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
Author
Shah, Saumil ; Srivastava, Ashish ; Sharma, Dushyant ; Sylvester, Dennis ; Blaauw, David ; Zolotov, Vladimir
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
2005
fDate
6-10 Nov. 2005
Firstpage
705
Lastpage
712
Abstract
This paper presents a novel approach towards the simultaneous Vt-assignment and gate-sizing problem. This inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. We prove that, under our formulation, the optimal solution has discrete Vts assigned to almost every gate, thus eliminating the need for a sophisticated snapping heuristic. We show that this technique performs dual-Vt assignment and gate sizing in a very efficient manner. Compared to a sensitivity based method, we achieve average leakage savings of 31% and average total power savings of 7.4% with very efficient runtimes.
Keywords
circuit optimisation; integrated circuit design; circuit nonlinear optimization; gate sizing; self-snapping continuous formulation; snapping heuristic; Availability; Circuits; Clustering algorithms; Computer industry; Lagrangian functions; Optimization methods; Runtime; Subthreshold current; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN
0-7803-9254-X
Type
conf
DOI
10.1109/ICCAD.2005.1560157
Filename
1560157
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