Quest for an NDT method to detect marginal ESD damage to ICs

The magnitude of the static charge built up in a typical working environment ranges from 100 volts to 20 kV. It this is discharged through an integrated circuit it may result in gate oxide breakdown in MOS devices and short or open circuits in metal tracks leading to device failure. Failure in TTL is due to breakdown of the reverse biased junction as a result of impact ionisation and subsequent Joule heating. To reduce the likelihood of static damage, special handling procedures are followed as prescribed by BS 5783. However the level of protection achieved is at best a function of how rigorously the guidelines are obeyed. A non-destructive test is described to evaluate an integrated circuits´ (IC) exposure to static damage events