Quest for an NDT method to detect marginal ESD damage to ICs

Author

Yates, R.B. ; Edwards, I.M.

Author_Institution

Sch. of Eng. Inf. Technol., Sheffield City Polytech., UK

fYear

1990

fDate

33023

Firstpage

42461

Lastpage

42464

Abstract

The magnitude of the static charge built up in a typical working environment ranges from 100 volts to 20 kV. It this is discharged through an integrated circuit it may result in gate oxide breakdown in MOS devices and short or open circuits in metal tracks leading to device failure. Failure in TTL is due to breakdown of the reverse biased junction as a result of impact ionisation and subsequent Joule heating. To reduce the likelihood of static damage, special handling procedures are followed as prescribed by BS 5783. However the level of protection achieved is at best a function of how rigorously the guidelines are obeyed. A non-destructive test is described to evaluate an integrated circuits´ (IC) exposure to static damage events

Keywords

electrostatic discharge; failure analysis; integrated circuit testing; nondestructive testing; 100 V to 20 kV; BS 5783; Joule heating; MOS devices; NDT method; TTL; device failure; gate oxide breakdown; handling procedures; impact ionisation; marginal ESD damage; metal tracks; open circuits; reverse biased junction; short circuits; static damage events; working environment;

fLanguage

English

Publisher

iet

Conference_Titel

NDT Evaluation of Electronic Components and Assemblies, IEE Colloquium on

Conference_Location

London

Type

conf

Filename

190282