Optimization of III-V FET architectures for high frequency and low consumption applications

To fulfill high-speed and low-power specifications for intelligent applications, III-V FETs (Field Effect Transistor) with high-gate dielectric stack are very appealing. Indeed, combining weak gate leakage of standard MOSFETs and good RF performance of HEMTs, they could enhance device scalability. Using full 2D Poisson-Schrödinger solver and then semi-classical Ensemble Monte Carlo device simulator, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Transistor) structures are investigated in terms of gate charge control and both static and dynamic I-V performance. In particular, Y parameters are carefully extracted from time-varying currents. This comparative study allows us to propose optimized nanoscale III-V FET with high-frequency performance under low power supply.