Title :
A 21/2-dimensional VLSI systolic array
Author_Institution :
Sch. of Inf. Syst., East Anglia Univ., Norwich, UK
Abstract :
A novel systolic array architecture, called the `21/ 2-dimensional systolic array´ (21/2-d SA), which has a pseudo-3-dimensional configuration among an array of processing cells, will be presented to overcome some of the shortcomings mentioned
Keywords :
VLSI; cellular arrays; digital signal processing chips; parallel architectures; 2 1/2 dimensional systolic array; VLSI; processing cells; pseudo-3-dimensional configuration; systolic array architecture;
Conference_Titel :
VLSI Signal Processing Architectures, IEE Colloquium on
Conference_Location :
London
