Dual-Threshold Voltage Technique for Asynchronous Pre-Charge Full Buffer Linear-Pipelines

Scaling the technology and reducing the feature size in integrated circuits have caused leakage power consumption to become one of the main challenges to the digital design. Dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Pre-Charge Full Buffer asynchronous linear-pipelines while still maintaining high performance. We employed Folded Dependency Graph to produce a formal performance analysis. In order to reduce leakage power an algorithm for assigning a high threshold voltage is proposed. Results obtained indicate that our proposed technique can achieve on average 30% savings for leakage power, while there is no performance penalty.