A high performance block floating point DSP chip-set

This paper describes the design and development of two ASICs which form the processing kernel of a high performance sonar signal processor; namely a 24-bit Block Floating Point Arithmetic Unit (BFPAU), and a Table Memory And Address Modifier (TMAAM). The system is based upon a 24-bit block floating point data format which is a compromise between fixed and floating point data; possessing the advantage of reducing the data storage requirement compared to true floating point while allowing arithmetic to be performed in the faster fixed-point format whilst retaining the extended dynamic range provided by floating point. The BFPAU and TMAAM perform the arithmetic processing; the BFPAU is the central arithmetic processor aimed at sonar signal processing in general and beamforming in particular, while the TMAAM provides a range of essential support functions such as look-up tables for trigonometric functions, address generation, exponent control and normalisation and program sequencing. Two blocks of dual-port RAM provide storage for system I/O data transfers, together with two blocks of RAM providing working data storage for the BFPAU. A block of video RAM is used to store address and control sequences for the processing element