DocumentCode :
2801777
Title :
Gate semi-around Si nanowire FET fabricated by conventional CMOS process with very high drivability
Author :
Sato, Soshi ; Lee, Yeonghun ; Kakushima, Kuniyuki ; Ahmet, Parhat ; Ohmori, Kenji ; Natori, Kenji ; Yamada, Keisaku ; Iwai, Hiroshi
Author_Institution :
Frontier Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
fYear :
2010
fDate :
14-16 Sept. 2010
Firstpage :
361
Lastpage :
364
Abstract :
Gate semi-around silicon nanowire (SiNW) FETs have been fabricated and their electrical characteristics, especially on the drivability, have been assessed for future high performance devices. Among different wire size, a SiNW FET with a cross-section of 12 × 19 nm2 has shown an improvement in the on-current (ION) when normalized by the channel peripheral length. A high ION over 1600 μA/μm at an overdrive voltage of 1 V has been achieved with a gate length and an oxide thickness of 65 and 3 nm, respectively. The origin of the high drivability has been speculated by higher carrier density, improved carrier mobility and the reduction in the series resistance.
Keywords :
CMOS integrated circuits; carrier density; carrier mobility; elemental semiconductors; field effect transistors; nanowires; silicon; CMOS process; Si; SiNW FET; carrier density; carrier mobility; gate semiaround nanowire FET; series resistance reduction; size 3 nm; size 65 nm; voltage 1 V; FETs; Logic gates; Oxidation; Shape; Silicon; Surface treatment; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Conference_Location :
Sevilla
ISSN :
1930-8876
Print_ISBN :
978-1-4244-6658-0
Type :
conf
DOI :
10.1109/ESSDERC.2010.5618212
Filename :
5618212
Link To Document :
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