DocumentCode
2801829
Title
Junctionless nanowire transistor (JNT): Properties and design guidelines
Author
Kranti, A. ; Yan, R. ; Lee, C.-W. ; Ferain, I. ; Yu, R. ; Akhavan, N. Dehdashti ; Razavi, P. ; Colinge, J.P.
Author_Institution
Tyndall Nat. Inst., Univ. Coll. Cork, Cork, Ireland
fYear
2010
fDate
14-16 Sept. 2010
Firstpage
357
Lastpage
360
Abstract
Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.
Keywords
MOSFET; nanowires; semiconductor doping; accumulation-mode MOS device; bulk conduction; conduction mechanism; current drive; doping concentration; gated resistor; inversion-mode MOS device; junctionless nanowire transistor; surface channel; threshold voltage; Doping; Junctions; Logic gates; MOSFETs; Neodymium; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Conference_Location
Sevilla
ISSN
1930-8876
Print_ISBN
978-1-4244-6658-0
Type
conf
DOI
10.1109/ESSDERC.2010.5618216
Filename
5618216
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