RTS amplitudes in decanano n-MOSFETs with conventional and high-k gate stacks

Low frequency (LF) noise in MOSFETs has been a topic of interest to both academia and industry in recent years. It is becoming a major concern for analogue circuit performance, DRAM operation, and will eventually impact critically upon the reliability of digital logic especially as devices continue to scale towards nano dimensions. Random telegraph signals (RTS) caused by the capture and emission of carriers in traps at the Si/SiO/sub 2/ interface have been posited as a major component of low frequency noise in semiconductor devices. The change in the drain current associated with trapping events in defect states is usually referred to as the RTS amplitude. The magnitude of the RTS amplitude is largest in the subthreshold regime at lower gate voltages and is reduced in the strong inversion regime as mobile charge in the inversion layer increasingly screens out the electrostatic influence of the trapped charge. We study the magnitude of the RTS amplitudes in nano-CMOS devices with conventional and high- gate stacks. Traps at the front and back gate dielectric interfaces, as well as traps in the body of the dielectric are considered. The impact of poly gate depletion is also taken into account.