Design of a Novel FSM Based Reconfigurable Multimode Interleaver for WLAN Application

In the recent past, the IEEE 802.11 based wireless LAN has emerged as a prevailing broadband indoor networking technology. Fast spread of wireless data communication systems and the ever increasing demand for faster data rates require quick design, implementation and test of new wireless algorithms for data communications. In this paper we present a novel technique to model the interleaver used in IEEE 802.11a and IEEE 802.11g based WLAN in VHDL using Xilinx ISE. Our proposed technique comprises of finite state machine (FSM) based address generator and FPGA´s internal resource based memory. The FSM based approach provides higher operating frequency and better FPGA resource utilization. Use of FPGA´s embedded memory offers advantages like reduced access time, lesser occupancy of circuit board and lower power consumption than external memory based techniques. The interleaver memory is modeled using two different types of embedded memory; one with dedicated and the other with distributed memory. Comparative analysis between the two techniques has been made in respect of use of FPGA´s internal resources, maximum operating frequency and power consumption. The simulation result obtained using ModelSim XE-III software is also presented.