Title :
Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study
Author :
Scarpellino, Michelangelo ; Singh, Ashwani ; Boutillon, Emmanuel ; Masera, Guido
Author_Institution :
Electron. Dept., VLSI Lab., Turin
Keywords :
Convolutional codes; Iterative decoding; Network topology; Network-on-a-chip; Parity check codes; Reconfigurable architectures; System-on-a-chip; Turbo codes; Very large scale integration; WiMAX;
Conference_Titel :
Spread Spectrum Techniques and Applications, 2008. ISSSTA '08. IEEE 10th International Symposium on
Conference_Location :
Bologna, Italy
Print_ISBN :
978-1-4244-2203-6
DOI :
10.1109/ISSSTA.2008.131
