• DocumentCode
    2802616
  • Title

    Wigner-function based simulation of classic and ballistic transport in scaled DG-MOSFETs using the Monte Carlo method

  • Author

    Gehring, A. ; Kosina, H.

  • Author_Institution
    Inst. for Microelectron., Tech. Univ. Vienna, Wien, Austria
  • fYear
    2004
  • fDate
    24-27 Oct. 2004
  • Firstpage
    227
  • Lastpage
    228
  • Abstract
    Double-gate (DG) MOS transistor structures have been proposed to boost the performance of scaled-down logic devices and to overcome some of the most severe problems encountered in bulk MOS field-effect transistors. However, with channel lengths below 25 nm. the question of the importance of quantum effects in the lateral direction, such as source-to-drain tunneling, arises. Frequently, ballistic transport is assumed which allows the device to be simulated using pure quantum-mechanical approaches. However, with carrier mean free paths in the range of several nanometers, scattering-limited transport may still be dominant which can be assessed using the Monte Carlo method by accounting for quantum-correction methods. An approach accounting for both, quantum interference phenomena and scattering processes, is based on the Wigner equation augmented by the Boltzmann collision operator. This equation can be solved using the Monte Carlo method. We report on the enhancement of the Wigner Monte Carlo simulator described by Kosina et al. (2002) for the simulation of silicon-based devices. The algorithm for annihilation of numerical particles now takes into account the multi-valley band structure of silicon. As test devices we use double-gate MOSFETs with gate lengths of 60 nm, 25 nm, and 10 nm.
  • Keywords
    MOSFET; Monte Carlo methods; ballistic transport; field effect transistors; logic devices; nanoelectronics; semiconductor device models; tunnelling; 10 nm; 25 nm; 60 nm; Boltzmann collision operator; Monte Carlo method; Wigner Monte Carlo simulator; Wigner-function based simulation; ballistic transport; bulk MOS field-effect transistors; carrier mean free paths; channel lengths; double-gate MOS transistor structures; logic devices; multivalley band structure; numerical particle annihilation; quantum effects; quantum interference phenomena; quantum-correction methods; quantum-mechanics; scaled DG-MOSFET; scattering processes; scattering-limited transport; silicon-based device simulation; source-to-drain tunneling; FETs; Logic devices; MOSFETs; Monte Carlo methods; Semiconductor device modeling; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on
  • Conference_Location
    West Lafayette, IN, USA
  • Print_ISBN
    0-7803-8649-3
  • Type

    conf

  • DOI
    10.1109/IWCE.2004.1407409
  • Filename
    1407409