DocumentCode :
2803019
Title :
Power-Aware Test Pattern Generation for At-Speed LOS Testing
Author :
Bosio, A. ; Dilillo, L. ; Girard, P. ; Todri, A. ; Virazel, A. ; Miyase, K. ; Wen, X.
Author_Institution :
LIRMM, Univ. of Montpellier II, Montpellier, France
fYear :
2011
fDate :
20-23 Nov. 2011
Firstpage :
506
Lastpage :
510
Abstract :
Launch-off-Capture (LOC) and Launch-off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In the literature, it has been shown that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. Power reduction seems to be the key to really exploit LOS test scheme. However, it has been proven that reducing too much test power can lead to test escape due to under-test. In this context, this study proposes a smart X-filling framework able to adapt peak power consumption during the launch-to-capture cycle according to the functional power, i.e. the power consumption of the circuit in functional mode. Here, the main goal is to obtain a final test set with peak power consumption as close as possible to the functional power. Experimental results, carried out on the well-known ITC´99 benchmarks, prove the feasibility of the proposed approach.
Keywords :
automatic test pattern generation; integrated circuit testing; power aware computing; at-speed LOS testing; at-speed scan delay testing; launch-off-capture; launch-off-shift; power-aware test pattern generation; Circuit faults; Clocks; Delay; Power demand; Support vector machine classification; Testing; Vectors; Cycle Average Power; LOC; LOS; Launch Power; Peak Power; TFC; Test Relaxation; X-filling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
ISSN :
1081-7735
Print_ISBN :
978-1-4577-1984-4
Type :
conf
DOI :
10.1109/ATS.2011.50
Filename :
6114726
Link To Document :
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