Testability of Cryptographic Hardware and Detection of Hardware Trojans

Cryptographic algorithms are routinely used toper form computationally intense operations over increasingly larger volumes of data, and in order to meet the high throughput requirements of the applications, are often implemented by VLSI designs. The high complexity of such implementations raises concern about their reliability. In order to improve upon the testability of sequential circuits, both at fabrication time and also in the field, Design For Testability (DFT) techniques are commonly employed. However conventional DFT methodologies for digital circuits have been found to compromise the security of the cryptographic hardware. In this tutorial we first discuss the challenges and potential attacks on cipher hardware through standard DFT techniques, and then potential solutions against them. Also, as the electronic design industry has grown globally, economic reasons dictate the widespread participation of external agents in modern design and manufacture of integrated circuits(ICs), which decreases the control that the IC design houses used to traditionally have over their own designs. This issue raises the question of ensuring Trust in an integrated circuit, and whether the IC can be certified to be free of malicious, hard-to detect circuitry, commonly referred to as Hardware Trojans. In this tutorial, we would explore the unique challenges and testing solutions to detect/prevent such malicious modifications.