Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS

This paper presents a new transistor model for modern deep sub-micron technologies where most existing textbook models fail. With only seven independent parameters in total the model is shown to be more accurate than the power law models in both linear and saturation regions. Up to 43% matching error reduction is observed with an industrial 90 nm technology. Moreover the model is first-order continuous. All these features make it attractive both for education and design analysis.