Title :
Experiences Teaching Physical Synthesis of FPGAs and ASICs
Author :
Bouldin, Don ; Chimakurthy, Pradeep
Author_Institution :
Univ. of Tennessee Knoxville, Knoxville
Abstract :
Interconnect delays dominate gate delays in integrated circuits fabricated using 180-nm feature sizes or below. Hence, no longer can designers separate the logic synthesis function from physical placement and routing but instead must perform physical synthesis to achieve timing closure with a minimum of design cycle iterations. Experiences teaching students to design competitive FPGAs and ASICs using physical synthesis are described in this paper.
Keywords :
application specific integrated circuits; electronic engineering education; field programmable gate arrays; integrated circuit interconnections; integrated circuit manufacture; logic design; teaching; ASIC; FPGA; design cycle iterations; gate delays; integrated circuits fabrication; interconnect delays; logic synthesis function; physical synthesis; Delay estimation; Education; Electronic design automation and methodology; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit synthesis; Libraries; Logic design; Routing; Timing;
Conference_Titel :
Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7695-2849-X
DOI :
10.1109/MSE.2007.39
