DocumentCode :
2803464
Title :
A Process Monitor Based Speed Binning and Die Matching Algorithm
Author :
Chakravarty, Sreejit
Author_Institution :
LSI Corp., Milpitas, CA, USA
fYear :
2011
fDate :
20-23 Nov. 2011
Firstpage :
311
Lastpage :
316
Abstract :
Speed binning groups ICs with similar performance and price point. Die matching matches dice with similar performance for system and 3D integration. A hybrid test flow combining process monitor readings and search using manufacturing test is presenteds. This flow eliminates error due to process monitor data inaccuracies and reduces test time of manufacturing test based search. Silicon data is presented.
Keywords :
elemental semiconductors; integrated circuit manufacture; integrated circuit testing; process monitoring; silicon; 3D integration; Si; die matching; hybrid test flow; manufacturing test; process monitor; silicon data; speed binning groups integrated circuit; Clocks; Equations; Frequency domain analysis; Mathematical model; Monitoring; Silicon; 3D Integration; Die Matching; Process Monitor; Speed Binning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
ISSN :
1081-7735
Print_ISBN :
978-1-4577-1984-4
Type :
conf
DOI :
10.1109/ATS.2011.96
Filename :
6114748
Link To Document :
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