DocumentCode :
2803679
Title :
An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic
Author :
Foist, Rod ; Ivanov, Andre ; Turner, Robin
Author_Institution :
Univ. of British Columbia, Vancouver
fYear :
2007
fDate :
3-4 June 2007
Firstpage :
127
Lastpage :
128
Abstract :
This paper presents a reference design and tutorial for an embedded PowerPC subsystem with user logic in a Xilinx Field Programmable Gate Array (FPGA). The design and tutorial were created to help graduate students who are doing research in complex electronic applications and want to prototype their designs in an FPGA. Specifically, the design provides a starting point for any application that requires an embedded processor plus user logic that is external to the processor block, but must interface to it. This design project provides a practical introduction to System-on- Chip (SOC) design, embedded processor design, hardware-software co-design, and general FPGA development. The design database and tutorial document can be downloaded from a website at The University of British Columbia (UBC).
Keywords :
embedded systems; field programmable gate arrays; hardware-software codesign; logic CAD; system-on-chip; FPGA design project; Xilinx field programmable gate array; design database; embedded PowerPC subsystem; embedded processor design; hardware-software co-design; processor block; system-on-chip design; tutorial document; user logic; Control systems; Field programmable gate arrays; Logic design; Physical layer; Process design; Programmable logic arrays; Prototypes; Read-write memory; Software prototyping; Wireless LAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7695-2849-X
Type :
conf
DOI :
10.1109/MSE.2007.22
Filename :
4231481
Link To Document :
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