DocumentCode
2803851
Title
Integrating Validation and Verification in the Digital Design Curriculum
Author
Yardi, Shrirang M. ; Hsiao, Michael S.
Author_Institution
Virginia Tech., Blacksburg
fYear
2007
fDate
3-4 June 2007
Firstpage
143
Lastpage
144
Abstract
This paper presents a module-based approach on integrating verification terminology, concepts and examples into the current computer engineering design curriculum. The primary goal is to equip students with the necessary verification and validation skills which are either ignored or are dealt with in an ad-hoc manner in current design courses. By making these courses verification-centric and emphasizing design-for-verifiability, we can produce highly qualified designers to handle the ever-larger and complex designs of the future.
Keywords
CAD; computer aided engineering; design for testability; educational courses; electronic engineering education; computer engineering design curriculum; design-for-verifiability; digital design curriculum; Combinational circuits; Debugging; Design engineering; Logic design; Logic devices; Programmable logic arrays; Programmable logic devices; Sequential circuits; Terminology; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Systems Education, 2007. MSE '07. IEEE International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-7695-2849-X
Type
conf
DOI
10.1109/MSE.2007.53
Filename
4231489
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