An Educational Tool for Design Automation of CMOS Cells

This paper presents a didactic tool that makes possible the automatic generation of full layouts of CMOS cells from its transistor level netlist in SPICE format. The tool allows the creation or modification of the netlist of a CMOS cell, including transistor sizing. It also let the user to quickly see the layout resulting after each modification. The tool does generate the cells in the linear matrix layout style and can automatically apply folding in the transistors when it is needed. Additionally, it is included a layout editor to allow the visualization of the generated layout.