Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs

With increasing scaling, it is common to find large SoCs with more than 40M bits of embedded SRAMs constituting more than 75% of total die area [1]. Physical design for such complex SoCs with high speed memories pose numerous challenges for both functional and memory BIST logic. In this paper, we focus on generating physical aware correct-by-constuct memory BIST data path for first pass physical design closure.