Testing and Design-for-Testability Techniques for 3D Integrated Circuits

Technology scaling for higher performance and lower power consumption is being hampered today by the bottleneck of interconnect lengths. 3D integrated circuits (3DICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming the interconnect bottleneck. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3Dintegration commercially viable. This paper presents a survey of test challenges for 3D ICs and describes recent innovations on various aspects of 3D testing and DfT. Topics covered include pre-bond testing (BIST and TSV probing), optimizations for post bond testing, and cost modeling for 3D integration and associated test flows.