DocumentCode
2804162
Title
Speedup of branch and bound method for hardware/software partitioning
Author
Strachacki, Marek
Author_Institution
Dept. of Microelectron. Syst., Tech. Univ. of Gdansk, Gdansk
fYear
2008
fDate
18-21 May 2008
Firstpage
1
Lastpage
4
Abstract
This paper presents sensitivity analysis of branch and bound (B&B) method used for hardware/software partitioning task. The impact of all B&B parameters on computation time is theoretically analyzed and results of experiments are presented. Results show that most sensitive parameters are a lower bound function, a selection rule, a branching rule and an initial solution. To shorten B&B computation time these parameters have to be set properly and additional pre-optimization step should be applied. This pre-optimization step uses simulated annealing to set parameters in limited time. Results of experiments show that the computation time speedup x130 is achieved on average. This hybrid optimization is the most efficient presented so far.
Keywords
hardware-software codesign; logic partitioning; sensitivity analysis; simulated annealing; tree searching; branch and bound method; hardware-software partitioning; optimization; sensitivity analysis; simulated annealing; Application specific integrated circuits; Computational complexity; Energy consumption; Field programmable gate arrays; Hardware; Logic devices; Sensitivity analysis; Simulated annealing; Space exploration; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology, 2008. IT 2008. 1st International Conference on
Conference_Location
Gdansk
Print_ISBN
978-1-4244-2244-9
Electronic_ISBN
978-1-4244-2245-6
Type
conf
DOI
10.1109/INFTECH.2008.4621608
Filename
4621608
Link To Document