• DocumentCode
    2804411
  • Title

    Evolutionary design of combinational digital circuits: State of the art, main problems, and future trends

  • Author

    Slowik, Adam ; Bialko, Michal

  • Author_Institution
    Dept. of Electron. & Comput. Sci., Koszalin Univ. of Technol., Koszalin
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper a state of the art, main problems and future trends concerning evolutionary design of combinational digital circuits are presented. Several evolutionary algorithms for design and optimization of combinational digital circuits are also shortly described. In evolutionary design methods the main problem is related to "combinatorial explosion" existing in those methods. Because evolutionary design methods are based on "generate and test" model, therefore together with growing of digital circuit input number, the number of potential combinations which must be tested are growing exponentially. This problem is a "bottle-neck" of those methods, and therefore it is discussed in details in this paper. To solve this problem it becomes important to elaborate efficient decomposition techniques of the designed circuits to some less complex sub-circuits, and then to design each of them independently. Also, it is important to create novel genetic operators (as mutation and crossover) which will always lead to acceptable solutions (solutions which satisfy the truth table). Due to such kind of operators, any repair mechanisms need not necessarily be used, and therefore the "generate and test" model will be simplified only to generation of new solutions, and therefore evolutionary design methods will become more effective.
  • Keywords
    combinational circuits; digital circuits; evolutionary computation; logic design; combinational digital circuit; decomposition technique; evolutionary algorithm; genetic operator; Algorithm design and analysis; Circuit testing; Combinational circuits; Design methodology; Design optimization; Digital circuits; Evolutionary computation; Logic gates; Minimization methods; Process design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Technology, 2008. IT 2008. 1st International Conference on
  • Conference_Location
    Gdansk
  • Print_ISBN
    978-1-4244-2244-9
  • Electronic_ISBN
    978-1-4244-2245-6
  • Type

    conf

  • DOI
    10.1109/INFTECH.2008.4621625
  • Filename
    4621625