Title :
A Partitioning Technique of General Combinational Circuit Into a Tree Type Circuit
Author_Institution :
Department of Electrical Engineering, North Carolina A & T State University
Keywords :
Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Computational complexity; Logic testing; Partitioning algorithms; Programmable logic arrays; Read only memory; Very large scale integration;
Conference_Titel :
System Theory, 1992. Proceedings. SSST/CSA 92. The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design
Print_ISBN :
0-8186-2665-8
DOI :
10.1109/SSST.1992.712205
