Title :
High-end server system partitioning for cost reduction
Author :
Katopis, George A. ; Zhou, Tingdong
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
In this work finite dimension integer programming for 2-core and 3-core chip designs is used to define the optimum number of processors in a SMP node (symmetric multi-processing) from the point of view of minimizing the number of the chips that cannot be used in the system even if they have functionally good PU cores on them. In effect the trade-offs between the PU cores on a chip, the number of PU on an SMP node, and the cost of the chip are studied. It is asserted that to the first order the cost of the chips is proportional to the scrap of chips with good cores on them that cannot be used in the implementation of the SMP nodes. The model shows that an optimized SMP offering can be defined so that the total chip cost of high-end server system can be reduced. This desired cost reduction limits the SMP node size for a given processor chip yield. It is shown that as the chip yields are improved, the SMP node size that can be profitably implemented can also be increased.
Keywords :
computer networks; cost reduction; integer programming; integrated circuit design; integrated circuit economics; integrated circuit yield; microprocessor chips; minimisation; multiprocessing systems; network servers; cost reduction; finite dimension integer programming; high end server system partitioning; minimization; multicore chip design; processor chip yields; symmetric multiprocessing node; Chip scale packaging; Companies; Computer industry; Cost function; Design optimization; High performance computing; Linear programming; Manufacturing; Testing; Timing;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2004. IEEE 13th Topical Meeting on
Print_ISBN :
0-7803-8667-1
DOI :
10.1109/EPEP.2004.1407528
